Uni-directional read/program non-volatile memory cells using floating gate for storage are well known in the art. See for example, U.S. Pat. No. 5,029,130, assigned to the present assignee. Typically, each of these types of memory cells uses a conductive floating gate to store one bit, i.e. either the floating gate stores charges or it does not. The charges stored on a floating gate control the conduction of charges in a channel of a transistor. In a desire to increase the storage capacity of such non-volatile memory cells, the floating gate of such memory cell is programmed to store some charges, with the different amount of charges stored being determinative of the different states of the cell, thereby causing a plurality of bits to be stored in a single cell. The problem with programming a cell to one of a multilevel state and then reading such a state is that the amount of charge stored on the floating gate differentiating one state from another must be very carefully controlled.
Bi-directional read/program non-volatile memory cells capable of storing a plurality of bits in a single cell are also well known in the art. See, for example, U.S. Pat. No. 6,011,725. Typically, these types of memory cells use an insulating trapping material, such as silicon nitride, which is between two other insulation layers, such as silicon dioxide, to trap charges. The charges are trapped near the source/drain also to control the conduction of charges in a channel of a transistor. The cell is read in one direction to determine the state of charges trapped near one of the source/drain regions, and is read in the opposite direction to determine the state of charges trapped near the other source/drain region. Hence, these cells are read and programmed bi-directionally. The problem with these types of cells is that to erase, holes or charges of the opposite conductivity must also be “programmed” or injected into the trapping material at precisely the same location where the programming charges were initially trapped in order to “neutralize” the programming charges. Since the programming charges and the erase charges are injected into a non-conductive trapping material, the charges do not move as in a conductive material. Therefore, if there is any error in injecting the erase charges to the location of the programming charges, the erase charges will not neutralize the programming charges, and the cell will not be completely erased. Moreover, to inject the erase charges, the cell must be erased bi-directionally, thereby increasing the time required for erasure of one cell.
The present invention is an improvement to the invention disclosed in U.S. patent application Ser. No. 10/409,333 published on Oct. 7, 2004, whose disclosure is incorporated herein by reference in its entirety. Although the present invention is an improvement to the aforementioned reference, the aforementioned reference is not prior art to the present invention since the present application is assigned to the same assignee as that reference.